Microchip Technology /ATSAME54P20A /SDHC0 /NISIER

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Interpret as NISIER

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MASKED)CMDC 0 (MASKED)TRFC 0 (MASKED)BLKGE 0 (MASKED)DMAINT 0 (MASKED)BWRRDY 0 (MASKED)BRDRDY 0 (MASKED)CINS 0 (MASKED)CREM 0 (MASKED)CINT

CINS=MASKED, BRDRDY=MASKED, CREM=MASKED, TRFC=MASKED, BWRRDY=MASKED, BLKGE=MASKED, DMAINT=MASKED, CMDC=MASKED, CINT=MASKED

Description

Normal Interrupt Signal Enable

Fields

CMDC

Command Complete Signal Enable

0 (MASKED): Masked

1 (ENABLED): Enabled

TRFC

Transfer Complete Signal Enable

0 (MASKED): Masked

1 (ENABLED): Enabled

BLKGE

Block Gap Event Signal Enable

0 (MASKED): Masked

1 (ENABLED): Enabled

DMAINT

DMA Interrupt Signal Enable

0 (MASKED): Masked

1 (ENABLED): Enabled

BWRRDY

Buffer Write Ready Signal Enable

0 (MASKED): Masked

1 (ENABLED): Enabled

BRDRDY

Buffer Read Ready Signal Enable

0 (MASKED): Masked

1 (ENABLED): Enabled

CINS

Card Insertion Signal Enable

0 (MASKED): Masked

1 (ENABLED): Enabled

CREM

Card Removal Signal Enable

0 (MASKED): Masked

1 (ENABLED): Enabled

CINT

Card Interrupt Signal Enable

0 (MASKED): Masked

1 (ENABLED): Enabled

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